This invention relates to a debugging technology and, more particularly, to a debugging system, a method for checking target programs to be executed by a data processor incorporated in a target system such as, for example, a facsimile and an image processing system and an information storage medium for storing a checking program.
It is rare for a target program to be installed in a target system such as a facsimile and an image processing system to correctly run jobs upon completion of the development. Usually, a debugging system runs the target program, and traces the target program to see how the instructions are sequentially executed, how the execution changes the contents of registers and what data codes are left in the addressable memory locations in a main memory. The debugging system stores the results of the tracing operation in a trace memory as pieces of trace data information indicative of errors in the target program, and a programmer eliminates the bugs from the target program.
FIG. 1 illustrates a prior art debugging system disclosed in Japanese Patent Publication of Unexamined Application (laid-open) No. 1-201740. The prior art debugging system comprises a main memory 1, a central processing unit 2 abbreviated as xe2x80x9cCPUxe2x80x9d, a read-only memory 3 abbreviated as xe2x80x9cROMxe2x80x9d, a trace controller 4 and a trace memory controller 5. An address bus and a data bus are shared between the main memory 1, the central processing unit 2, the read only memory 3, the trace controller 4 and the trace memory controller 5, and the main memory 1, the central processing unit 2, the read only memory 3, the trace controller 4 and the trace memory controller 5 communicate with one another through the address/data buses.
The main memory 1 stores a target program to be checked, and the instruction codes of the target program are assigned addresses, respectively. The central processing unit 2 sequentially fetches instruction codes from the main memory 1, and runs the target program so as to control component parts of the target system (not shown). While the central processing unit 2 is running the target program, the central processing unit 2 supplies an address data signal representative of the next address assigned to the instruction code to be executed to the trace controller 4. The read-only memory 3 stores three kinds of address information as shown in FIG. 2. The first kind of address information represents trigger addresses At/Bt/Ct/ . . . , the second kind of address information represents high-limit trace addresses Ah/Bh/Ch/ . . . , and the third kind of address information represents low-limit trace addresses Al/Bl/Cl/ . . . The read only memory 3 supplies address data signals respectively representative of the trigger address At/Bt/Ct/ . . . , the high-limit trace address Ah/Bh/Ch/ . . . and the low-limit trace address Al/Bl/Cl/ . . . to the trace controller 4.
Turning back to FIG. 1 of the drawings, the trace controller 4 includes a trigger address detector 6, a high-limit trace address detector 7, a low-limit trace address detector 8 and an AND gate 9. The AND gate 9 is connected to the trace memory controller 5, and supplies a trace enable signal thereto. The trace controller 4 instructs the trace memory controller 5 to start the tracing operation through the trace enable signal. The address data signal representative of the trigger address At/Bt/Ct/ . . . reaches the trigger address detector 6, and the central processing unit 2 supplies the address data signal representative of the next address assigned to the instruction code to be executed to the trigger address detector 6. The trigger address detector 6 determines a trigger point from the address data signals, and produces a trigger address detection signal representative of the trigger point to the read only memory 3.
The address data signal representative of the high-limit trace address Ah/Bh/Ch/ . . . reaches the high-limit trace address detector 7, and the central processing unit 2 further supplies the address data signal representative of the next address assigned to the instruction code to be executed to the high-limit trace address detector 7. The high-limit trace address detector 7 checks the address data signals to see whether or not the next address exceeds the high-limit address. When the next address does not exceed the high-limit address, the high-limit trace address detector 7 changes a detecting signal to an active level, and supplies the detecting signal to the AND gate 9. On the other hand, if the next address exceeds the high-limit address, the high-limit trace address detector 7 keeps the detecting signal inactive.
The address data signal representative of the high-limit trace address Al/Bl/Cl/ . . . reaches the low-limit trace address detector 8, and the central processing unit 2 further supplies the address data signal representative of the next address to the low-limit trace address detector 8. The low-limit trace address detector 8 checks the address data signals to see whether or not the next address reaches an address value less than that the low-limit address. When the next address falls within the address range defined by the high-limit address and the low-limit address, the low-limit trace address detector 8 changes a detecting signal to an active level, and supplies the detecting signal to the AND gate 9. On the other hand, if the next address is lower than the low-limit address, the low-limit trace address detector 8 keeps the detecting signal inactive.
The detecting signals are supplied from the high-limit trace address detector 7 and the low-limit trace address detector 8 to the AND gate 9. When both detecting signals are active, the AND gate 9 yields the trace enable signal of the active level, and supplies the trace enable signal to the trace memory controller 5. With the trace enable signal of the active level, the trace memory controller 5 starts the tracing, and stores the pieces of trace data information in a built-in memory (not shown).
The prior art debugging system behaves as follows. The trigger address At is read out from the read only memory 3, and is transferred to the trigger address detector 6. The high-limit trace address Ah is further read out from the read only memory 3, and is transferred to the high-limit trace address detector 7. The low-limit trace address Al is further read out from the read only memory 3, and is transferred to the low-limit trace address detector 8. Thus, the trigger address At, the high-limit trace address Ah and the low-limit trace address Al are stored in the trigger address detector 6, the high-limit trace address detector 7 and the low-limit trace address detector 8, respectively.
Subsequently, the central processing unit 2 sequentially fetches the instruction codes of the target program, and executes them. Various control signals are produced through the execution, and the component parts of the target system (not shown) are controlled with the control signals. While the central processing unit 2 is running the target program, the central processing unit 2 produces the address data signal representative of the next address assigned to the instruction code presently executed and data signals supplied to the target system. The address data signal is supplied through the address bus to the main memory 1 and the data signals to the target system. The central processing unit 2 further supplies the address data signal to the trigger address detector 6, the high-limit trace address detector 7 and the low-limit trace address detector 8. The high-limit trace address detector 7 and the low-limit trace address detector 8 respectively compare the next address with the high-limit trace address and the low-limit trace address to see whether or not the next address falls within the address range defined by the high-limit trace address and the low-limit trace address. If the next address falls within the address range, the AND gate 9 supplies the trace enable signal of the active level to the trace memory controller 5.
With the trace enable signal of the active level, the trace memory controller 5 starts to take the address data signal on the address bus and the data signals on the data bus, and accumulates the pieces of trace data information in a built-in trace memory (not shown). Thus, the trace memory controller 5 carries out a tracing operation. When the next address exits from the address range, the AND gate 9 changes the trace enable signal to the inactive level, and the trace memory controller 5 interrupts the tracing operation.
When the next address reaches the trigger address At, the trigger address detector 6 produces the trigger address detecting signal. The trigger address detecting signal is supplied to the read only memory 3. The read only memory 3 is responsive to the trigger address detecting signal so as to transfer the next trigger address Bt, the next high-limit trace address Bh and the next low-limit trace address Bl to the trigger address detector 6, the high-limit trace address detector 7 and the low-limit trace address detector 8, respectively. The trace controller 4 changes the trace enable signal to the active level, and supplies it to the trace memory controller 5. Then, the trace memory controller 5 requests the central processing unit 3 to transfer pieces of trace data information to the built-in trace memory (not shown), and stores the pieces of trace data information therein.
The trace memory controller 5 accumulates the pieces of trace data information between the low-limit trace address Al and the high-limit trace address Ah in the built-in trace memory until the central processing unit 2 supplies the next address consistent with the trigger address At. Similarly, the trace memory controller 5 accumulates the pieces of trace data information between the low-limit trace address Bl and the high-limit trace address Bh in the built-in trace memory until the central processing unit 2 supplies the next address consistent with the trigger address Bt. Thus, the prior art debugging system freely changes the address range during the tracing operation.
In the prior art debugging system, the address bus and the data bus are connected to the trace controller 4 and the trace memory controller 5 as well as the central processing unit 2, and the trace memory controller 5 accumulates the pieces of trace data information in the built-in trace memory of the trace memory controller 5. The central processing unit 2 has been developed, and a latest central processing unit is responsive to a clock frequency of hundreds mega-heltz. In this situation, the trace controller 4 and the trace memory controller 5 are connected to the address bus and the data bus through a connector and/or probes. The connector and/or probes increase the parasitic capacitance coupled to the address bus and the data bus, and the large parasitic capacitors deform the waveform of the address/data signals during the propagation along the address/data buses. This results in malfunction of the target system.
If a cache memory is incorporated in the central processing unit 2, the central processing unit 2 directly fetches an instruction code from the cache memory without transfer of the address data signal to the main memory 1, and produces the data signals. The trace memory controller 5 monitors the address bus and the data bus, only, and can not monitor the internal address signal lines in the central processing unit 2. For this reason, the address assigned to the instruction code directly transferred from the cache memory does not form a part of the trace data information.
If a tracing circuit and an associated memory are added to the central processing unit with the built-in cache memory, the missing addresses are supplied from the associated memory through the address bus to the trace memory controller 5, and the above-described problem would be solved. This means that development of the central processing unit with the tracing circuit and the associated memory is required for the debugging system. However, problems are encountered in the usage of such a newly developed central processing unit. First, the development cost is great. Second, the debugging system checks the target program for errors in the circumstances different from those in an actual target system. For this reason, it is better to add circuits and memories required for the tracing to the standard central processing unit 2 incorporated in the actual target system.
Although the prior art debugging system shown in FIG. 1 has the above-described problems, it is possible to increase the built-in trace memory as large as possible. If a high-speed memory device is used for the built-in trace memory, the pieces of trace data information are accumulated in the built-in trace memory in a real time fashion. However, if a large built-in trace memory is integrated on the semiconductor chip for the central processing unit 2, the large built-in cache memory occupies wide area, and enlarges the semiconductor chip for the central processing unit. This results in cost-up.
If the address/data signals are directly taken out from the central processing unit through signal pins exclusively used in the tracing operation to the outside thereof, the debugging system may accumulate all the pieces of trace data information. However, the signal pins exclusively used in the tracing operation are causative of enlargement of the package for the central processing unit, and are wasteful. Moreover, it is technically difficult to accumulate the pieces of trace data information in a trace memory outside of the package for the central processing unit at the data storing speed equal to the data processing speed.
The trigger conditions and the tracing conditions are previously given to the prior art debugging system so as to define the address ranges to be traced. For this reason, the pieces of trace data information are reduced rather than pieces of trace data information without definition of the address ranges. However, a target program may contain a conditional branch instruction for frequently transferring the control to a loop and/or branch instructions for frequently transferring the control between the main routine and sub-routines at a short time period. If the conditional branch instruction or the branch instructions fall within the address range, the pieces of trace data information are drastically increased due to the loop and/or the sub-routines. In this situation, even if the central processing unit 2, the read only memory 3, the trace controller 4 and the trace memory controller 5 are integrated on a single semiconductor chip, the trace memory merely offers a small data storage capacity, and the pieces of trace data information overflow from the trace data memory. When the overflow takes place, the debugging system interrupts the tracing operation, and reads out all the pieces of trace data information from the trace memory to the outside of the semiconductor chip. Thereafter, the debugging system restarts the tracing operation. As a result, the debugging system can not check the target program in the real time fashion.
As will be understood from the foregoing description, the above-discussed solutions are not feasible. Although the prior art debugging system shown in FIG. 1 has several advantages over the central processing unit with the built-in tracing circuit and the central processing unit with the exclusively used signal pins and so forth, the problems are encountered in the malfunction of the target system due to the deformation of the signal waveform and in the missing trace data information.
It is therefore an important object of the present invention to provide a debugging system, which economically accumulates pieces of trace data information in a real time fashion without any malfunction of a target system.
It is also an important object of the present invention to provide a method for checking a target program, which is used in the debugging system.
It is also an important object of the present invention to provide an information storage medium, which stores a computer program for the method for checking a target program.
To accomplish the object, the present invention proposes to select pieces of trace data information to be required before storing a temporary data storage.
In accordance with one aspect of the present invention, there is provided a tracing system for acquiring pieces of trace data information representative of a history during an execution of a target program by a central processing unit, and the tracing system comprises a temporary data storage temporarily storing predetermined pieces of trace data information and outputting the predetermined pieces of trace data information, a data storage connected to the temporary data storage for storing the predetermined pieces of trace data information, a trace condition storage for storing at least one trace condition representative of the predetermined pieces of trace data information to be required, a trace operation initiator for storing at least a starting point of a tracing operation and a tracer connected to the temporary data storage, the trace condition storage and the trace operation initiator, starting the tracing operation at the starting point so as to extract pieces of trace data information from pieces of status data information generated by the central processing unit during the execution of the target program, select the predetermined pieces of trace data information from the pieces of trace data information in accordance with the tracing condition and supply the predetermined pieces of trace data information to the temporary data storage.
In accordance with another aspect of the present invention, there is provided a method for checking a target program comprising the steps of a) determining a tracing condition representative of predetermined pieces of trace data information to be required and a starting point at which a tracing operation is initiated, b) running the target program so as to successively generate pieces of status data information representative of a history during an execution of the target program by a central processing unit, c) starting a tracing operation at the starting point so as to extract pieces of trace data information from the pieces of status data information, d) comparing the pieces of trace data information with the tracing condition so as to select the predetermined pieces of trace data information from the pieces of trace data information, e) storing the predetermined pieces of trace data information in a temporary data storage and f) transferring the predetermined pieces of trace data information to a data storage.
In accordance with yet another aspect of the present invention, there is provided an information storage medium for storing a computer program representative of a method for checking a target program, and the method comprises the steps of a) determining a tracing condition representative of predetermined pieces of trace data information to be required and a starting point at which a tracing operation is initiated, b) running the target program so as to successively generate pieces of status data information representative of a history during an execution of the target program by a central processing unit, c) starting a tracing operation at the starting point so as to extract pieces of trace data information from the pieces of status data information, d) comparing the pieces of trace data information with the tracing condition so as to select the predetermined pieces of trace data information from the pieces of trace data information, e) storing the predetermined pieces of trace data information in a temporary data storage and f) transferring the predetermined pieces of trace data information to a data storage.